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NXP Semiconductors
LPC11C12/C14
7.16.5.2
7.16.5.3
Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks can be shut
down for increased power savings. The user can configure the Deep-sleep mode to a
large extent, selecting any of the oscillators, the PLL, BOD, the ADC, and the flash to be
shut down or remain powered during Deep-sleep mode. The user can also select which of
the oscillators and analog blocks will be powered up after the chip exits from Deep-sleep
mode.
The GPIO pins (13 pins total) serve as external wake-up pins to a dedicated start logic to
wake up the chip from Deep-sleep mode.
The timing of the wake-up process from Deep-sleep mode depends on which blocks are
selected to be powered down during deep-sleep.
For lowest power consumption, the clock source should be switched to IRC before
entering Deep-sleep mode, all oscillators and the PLL should be turned off during
deep-sleep, and the IRC should be selected as clock source when the chip wakes up from
deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock
signal after start-up.
If power consumption is not a concern, any of the oscillators and/or the PLL can be left
running in Deep-sleep mode to obtain short wake-up times when waking up from
deep-sleep.
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11C12/C14 can wake up from Deep power-down mode via the
WAKEUP pin.
7.17 System control
7.17.1 Reset
Reset has four sources on the LPC11C12/C14: the RESET pin, the Watchdog reset,
power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage
attains a usable level, starts the IRC and initializes the flash controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.17.2 Brownout detection
The LPC11C12/C14 includes four levels for monitoring the voltage on the V DD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
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